Taichi Ishitani

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Jagan Joined on Dec 7, 2019 https://github.com/taichi-ishitani

Education

Doshisha Univ.

Work

Processor Verification Engineer at PEZY Computing K.K.

tnoc

Network on Chip Implementation written in SytemVerilog

SystemVerilog • 129 stars

tbcm

Basic Common Modules

SystemVerilog • 9 stars

tue

Useful UVM extensions

SystemVerilog • 18 stars

tvip-axi

AMBA AXI VIP

SystemVerilog • 293 stars

Ruby/SystemVerilog/UVM

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Oct 8

YPS: YAML Positioning System

#ruby #rails

1 min read