Forem: Talal Ahmad

The Hidden Cost of Every Query You Send

Talal Ahmad — Sun, 17 May 2026 10:03:45 +0000

AI's energy problem is real, it's growing, and it's showing up in your electricity bill.

Photo by Paul Hanaoka on Unsplash

Here is a number that you should know.

In 2024, US data centres consumed 183 terawatt-hours of electricity. That is more than 4% of the entire country's electricity consumption — roughly equivalent to the annual electricity demand of the entire nation of Pakistan.

And that was before the AI boom fully hit.

In 2025, electricity demand from data centres soared by 17%, with AI-focused facilities climbing even faster — well outpacing global electricity demand growth of 3%. By 2030, worldwide data centre consumption is projected to nearly double, from 448 TWh to 980 TWh. AI-optimised servers alone are set to grow almost fivefold — from 93 TWh to 432 TWh.

This is not a background statistic. It is a civilisational choice we are making quietly, one GPU cluster at a time.

What a Single Query Actually Costs

Action	Energy per query
Google Search	~0.0003 kWh
ChatGPT text query	~0.0003 kWh (0.3 Wh)
Image generation	Estimated 10–100x text
AI agent (multi-step)	Compounding per step

A ChatGPT query consumes roughly 0.3–0.34 watt-hours of electricity — about ten times more than a Google search. That sounds small. Multiply it by hundreds of millions of daily users, add image generation, video, AI agents running autonomously in the background — and the numbers become difficult to comprehend.

AI-focused data centres consumed 155 TWh in 2025. All of the world's text queries accounted for around 2% of that. The other 98% went to training, fine-tuning, and infrastructure overhead.

The query on your screen is the smallest part of the problem.

Who Pays for It

The obvious answer is Big Tech. The less obvious answer is you.

Residential electricity prices jumped 7.1% in 2025 — more than double the inflation rate — and topped 20% in some states. The AI data centre rush is a significant contributing factor, because hyperscale data centres demand a nearly unimaginable amount of energy. A typical hyperscale facility uses around 100 MW — as much as 100,000 households. Meta's Hyperion project in Louisiana will need at least 5 GW to run.

In Ireland, data centres now consume 22% of the country's total electricity. A small country's grid, quietly colonised by server racks.

Regions such as Virginia and Ireland may experience grid vulnerability, as AI infrastructure is highly concentrated — over 90% of projected compute capacity sits in North America, Western Europe, and Asia-Pacific. The burden is not evenly distributed. The benefits are even less so.

The Fixes Engineers Are Actually Building

Neuromorphic Chips

Neuromorphic chips abandon the von Neumann architecture entirely — no clock, no fetch-decode-execute cycle, no power consumed when nothing is happening. Intel's Loihi 2 has demonstrated 1,000x energy reduction on certain tasks versus a GPU. Researchers have trained a 1.5-billion-parameter model on neuromorphic hardware, achieving up to a 70,000-fold reduction in energy consumption and a 100-fold speed-up compared with GPUs.

Photonic Chips

Photonic chips replace electrical signals with light. By eliminating electronic-to-optical signal conversions and achieving seamless communication through wavelength division multiplexing, photonic systems significantly reduce energy consumption in data centres. Integrating analog memory into neuromorphic photonic architectures can achieve over 26x power savings compared to conventional SRAM-DAC designs.

Nuclear and Renewables

The pipeline of conditional agreements between data centre operators and small modular reactor projects has grown from 25 GW at end of 2024 to 45 GW — indicating that AI's energy appetite may accelerate the commercialisation of entirely new energy technologies.

The Uncomfortable Truth

Power consumption per AI task is declining rapidly — efficiency is improving at a rate unprecedented in energy history. The chips are getting better. The models are getting more efficient.

But more people are using AI. More tasks are being handed to AI agents. The efficiency gains are being consumed faster than they are being made.

This is Jevons' Paradox — the more efficient a technology becomes, the more it gets used, and total consumption rises. It happened with steam engines. With cars. With electricity itself.

The question is not whether AI will become more energy efficient. It will. The question is whether the hardware revolution — neuromorphic, photonic, the entire post-silicon stack — can outrun the appetite of a technology the world has decided it cannot live without.

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References

👀 Next Article Preview — AI's Energy Problem

Talal Ahmad — Fri, 15 May 2026 06:24:46 +0000

Quick heads up: my next deep dive is dropping soon.

The Hidden Cost of Every Query You Send

Some numbers I couldn't stop thinking about while researching:

A ChatGPT query uses 10x more energy than a Google search
US data centres consumed as much electricity as all of Pakistan in 2024
98% of AI data centre energy goes to training and infrastructure — not your query
Ireland's data centres now consume 22% of the country's total electricity

The article covers:

The actual scale of the problem with real IEA/Gartner numbers
The grid stress hitting Virginia, Ireland, and Oregon right now
Neuromorphic chips achieving 70,000x energy reduction vs GPUs in research
Photonic chips and why light beats copper at data centre scale
Why Jevons' Paradox means efficiency gains alone won't save us

Follow me on Dev.to to catch it when it drops.

Anything specific you want me to go deeper on? Drop it in the comments.

After Silicon: The Technologies That Will Power the Next Era of Computing

Talal Ahmad — Thu, 14 May 2026 21:48:45 +0000

From atomic-scale transistors to chips made of light — here is what comes after the 2nm revolution, and why it matters for everything from your smartphone to artificial general intelligence.

Photo by Laura Ockel on Unsplash

In Q4 2025, TSMC confirmed volume production of its N2 node. At 2nm, transistor gates are approximately 10 silicon atoms wide. That is not a metaphor for "very small" — it is a regime where quantum tunnelling, variability at the atomic scale, and statistical dopant fluctuations are no longer edge cases. They are the design constraints.

The engineering community has spent decades treating Moore's Law as a roadmap. What comes next is not one road. It is six, running in parallel.

1. Gate-All-Around (GAA) Transistors

FinFETs gave the gate three sides of control over the channel. GAA wraps it around all four sides of horizontally stacked silicon nanosheets — typically 5–8 ribbons, each 5nm thick, separated by high-k dielectric.

The physics: improved electrostatic gate control means steeper subthreshold slope, lower off-state leakage current (I_off), and the ability to tune drive current (I_on) by adjusting nanosheet width at the mask level — something FinFETs could not do without a full process change.

TSMC N2: 10–15% speed gain at iso-power, or 25–30% power reduction at iso-performance vs N3E. Gate pitch ~45nm, metal pitch ~24nm.

Intel 18A: Combines RibbonFET (GAA) with Backside Power Delivery Network (BSPDN) — PowerVia. Routing Vdd and Vss on the back of the wafer eliminates IR drop from power rails competing with signal routing on the front. Result: ~6% performance gain from BSPDN alone, plus freed routing tracks for signal density.

Samsung SF3: Implemented GAA at 3nm in 2022 — earliest production GAA — but yield challenges limited the advantage. SF2 (2nm-class) targets correction in 2025.

Next milestones: TSMC A16 (backside power + GAA, 2027), Intel 14A (first High-NA EUV in full production, 2027), IMEC roadmap to "A2" — 2 angstroms — by 2036.

2. 3D Integration: Chiplets and Hybrid Bonding

Monolithic scaling hits yield walls fast — defect density is roughly constant per unit area, so doubling die area roughly halves yield. Chiplets solve this by partitioning a design into smaller dies, each manufactured at the process node best suited to it, then integrated in-package.

The interconnect hierarchy matters:

Interconnect Type	Bump Pitch	Bandwidth Density
Organic substrate	~100µm	~1 GB/s/mm²
Silicon interposer (CoWoS)	~10µm	~1 TB/s/mm²
Hybrid bonding (SoIC, Foveros Direct)	~1µm	~10+ TB/s/mm²

At 1µm hybrid bond pitch, a 100mm² interface carries ~1 Pb/s of theoretical bandwidth — orders of magnitude beyond anything a PCIe or HBM interface achieves off-package.

Nvidia's Blackwell B100 connects two reticle-limited dies via NV-HBI at 10 TB/s with ~900 GB/s of HBM3e memory bandwidth. The future AI accelerator likely stacks a logic die (leading-edge node), HBM (DRAM-optimised node), and a photonics die (specialised process) — heterogeneous integration as the norm.

3. Silicon Photonics and Co-Packaged Optics

The bandwidth-per-watt of copper interconnects degrades sharply beyond ~1–2m. At rack scale in AI clusters, this is the bottleneck — not the GPU.

Silicon photonics builds optical components — ring modulators, Mach-Zehnder interferometers, germanium photodetectors, grating couplers — on standard 300mm CMOS wafers. Data modulates onto light at 50–100 Gbps per wavelength; WDM stacks 8–32 wavelengths per fibre, reaching multi-Tbps per physical link.

Co-Packaged Optics (CPO) eliminates the pluggable transceiver entirely — the optical engine is wire-bonded or hybrid-bonded directly to the switch ASIC. Nvidia's Quantum-X800 and Spectrum-X800, launched in 2026, use CPO at 100–400 Tb/s aggregate, with 3.5x power efficiency improvement and 10x signal integrity improvement vs pluggable modules.

At rack scale, the bottleneck in AI computing is not the GPU — it is the copper wire. Light carries data at the speed of, well, light.

The research frontier: all-optical neural networks where matrix-vector multiplications — the core operation in transformer inference — are performed optically at the speed of light with near-zero dynamic power. MIT and University of Strathclyde groups are the ones to watch.

4. Wide-Bandgap Semiconductors: GaN and SiC

Silicon has a bandgap of ~1.1 eV. That limits its breakdown voltage, thermal conductivity, and electron saturation velocity. Wide-bandgap materials change those limits entirely:

Property	Si	GaN	SiC
Bandgap (eV)	1.1	3.4	3.3
Breakdown field (MV/cm)	0.3	3.3	2.5
Electron mobility (cm²/Vs)	1400	2000 (2DEG)	900
Thermal conductivity (W/mK)	150	230	490

GaN exploits a 2D electron gas (2DEG) at the AlGaN/GaN heterojunction — a high-density, high-mobility channel that enables HEMT transistors switching at RF frequencies (mmWave 5G, radar) and power conversion at >90% efficiency.

SiC MOSFETs handle 650V–3.3kV switching for EV traction inverters, industrial motor drives, and grid infrastructure. SiC inverter switching losses are ~50% lower than equivalent silicon IGBTs. SiC market CAGR projected at >20% through 2030.

5. 2D Materials: Graphene and TMDs

The IEEE roadmap identifies 2D materials as the primary candidate for sub-1nm channel materials — at monolayer thickness (~0.3nm for MoS₂), the channel is physically immune to short-channel effects that plague thin-body silicon at equivalent dimensions.

Graphene: Zero bandgap limits its use as a transistor channel, but electron mobility (~200,000 cm²/Vs suspended, ~10,000–50,000 cm²/Vs on substrate) makes it exceptional for interconnects. Copper resistivity increases sharply below ~10nm wire width due to surface and grain boundary scattering. Graphene interconnects show 100x higher current density than copper at equivalent dimensions.

TMDs (MoS₂, WSe₂, WS₂): Semiconducting 2D materials with bandgaps of 1.0–2.0 eV at monolayer thickness. TSMC's research division has demonstrated stacked nanosheet GAA transistors with monolayer MoS₂ channels integrated into the exact architecture defining N2.

In 2025, a research team published a bismuth-based transistor at 0.1nm (angstrom node) — 40% faster and 3x more energy-efficient than leading silicon nodes in benchmarks.

Before graphene powers entire systems, it will make its impact in interconnects — the first real silicon-graphene hybrid applications are closer than most engineers think.
— Semiconductor Engineering, 2025

6. Neuromorphic Computing

Von Neumann architecture has a fundamental inefficiency: the memory wall. Every operation requires data to move between processor and memory — energy spent on data movement often exceeds energy spent on computation itself.

Neuromorphic chips co-locate memory and processing. Artificial neurons integrate input spikes over time; when membrane potential crosses threshold, they fire — asynchronous, event-driven, sparse. No clock. No fetch-decode-execute. Power consumption proportional to activity, not clock rate.

Intel Loihi 2: 1 million neurons, 120 million synapses. Demonstrated 1,000x energy reduction vs GPU on certain combinatorial optimisation problems.

Photonic neuromorphic: A VCSEL with optical feedback implements a leaky integrate-and-fire neuron at GHz spike rates — six orders of magnitude faster than biological neurons. University of Strathclyde demonstrated GHz-rate VCSEL spiking networks in 2023.

The convergence target: neuromorphic processors for sparse edge inference + quantum coprocessors for optimisation + classical cores for control flow. Heterogeneous in architecture, not just process node.

The Roadmap

Timeframe	Milestones
2025–2026	GAA volume production (TSMC N2, Intel 18A). CPO switches (Nvidia). GaN/SiC mainstream.
2027–2028	TSMC A16 + backside power. Intel 14A + High-NA EUV. Rapidus 2nm. First commercial photonic AI accelerators. HBM4 widespread.
2029–2032	Sub-1nm nodes. 2D material transistors in pilot production. Graphene interconnects in leading-edge logic. Neuromorphic at edge scale.
2033–2036+	IMEC A2 (2 angstrom). Photonic-electronic co-integration standard. Quantum-classical hybrid systems commercial.

Why It Matters for What We Build

The software abstractions we write against — memory models, compute primitives, communication layers — are all downstream of hardware architecture. As the hardware layer fragments into heterogeneous stacks of logic, memory, photonics, and neuromorphic accelerators, the programming models will have to follow.

The engineers who understand what is physically happening at the transistor, interconnect, and package level will be the ones who extract real performance from what comes next — not just call an API and hope.

If this was useful, drop a ❤️ or 🦄 — it helps others find the article.

Have a question about any of these technologies or want me to go deeper on one? Drop it in the comments — I read and reply to all of them.

Follow me here on Dev.to for more deep dives on semiconductor technology, AI hardware, and the engineering behind next-gen computing.