Forem: AtlasPCBEngineering

ASE, Samsung, and Amkor Accelerate Packaging Capacity Race: $15B+ in New Facilities for 2026-2027

AtlasPCBEngineering — Sat, 09 May 2026 06:15:41 +0000

Packaging Giants Launch Unprecedented Expansion Wave

April-May 2026 — The global semiconductor packaging and testing sector has entered its most aggressive capacity expansion phase in history. Since early 2026, the three largest OSAT (Outsourced Semiconductor Assembly and Test) companies have collectively announced over $15 billion in new facility investments, driven by insatiable demand from AI accelerators, HPC systems, and advanced automotive electronics.

The expansion comes as advanced packaging—particularly chiplet integration, 2.5D/3D stacking, and co-packaged optics—has become the primary pathway for chip performance improvement as Moore's Law transistor scaling slows.

ASE: Six New Facilities in One Year

On April 10, 2026, ASE Technology Holding broke ground on a new facility in Kaohsiung's Renwu Industrial Park, Taiwan, with total investment exceeding TWD 108.3 billion (~$3.4B USD). The plant will focus on advanced semiconductor testing services for AI, HPC, 5G communications, and automotive electronics applications.

Phase one completion is scheduled for April 2027, with phase two operational by October 2027. The facility is projected to generate annual output value of up to TWD 177.3 billion once fully ramped.

But this Kaohsiung facility represents only one piece of ASE's global puzzle. CEO Tien Wu stated that 2026 marks the company's most aggressive year for fab construction ever, with six new plants breaking ground worldwide—a company record. Additional expansion projects span:

United States — Addressing reshoring demand for defense and automotive
Malaysia — Expanding existing Penang operations for consumer electronics
Japan — Supporting Japanese semiconductor revival ecosystem
Germany — Serving European automotive OEMs requiring local packaging

ASE initially budgeted $7 billion in capital expenditure for 2026 but indicated potential upward revision due to stronger-than-expected market demand.

On the technology front, Wu confirmed that co-packaged optics (CPO) is entering mass production in 2026—a critical technology for next-generation AI data center interconnects that places extreme demands on substrate quality and packaging precision.

Samsung: $4 Billion Vietnam Packaging Plant

According to Bloomberg (April 10, 2026), Samsung Electronics plans to invest $4 billion to build a semiconductor packaging and testing facility in Thai Nguyen Province, northern Vietnam. The investment represents Samsung's strategic bet on Vietnam as a major packaging hub, leveraging:

Lower labor costs compared to South Korea
Established Samsung manufacturing ecosystem in Vietnam (smartphones, displays)
Geographic proximity to China-based customers while diversifying from China
Vietnam's growing engineering talent pool and favorable trade agreements

The facility will target both Samsung's internal packaging needs and potential third-party OSAT services, positioning Vietnam as a serious alternative to traditional packaging hubs in Taiwan and Malaysia.

Amkor: Doubling Down on Vietnam

Simultaneously, Amkor Technology is accelerating its own Vietnam capacity expansion. Having already established operations in the country, Amkor is investing in additional advanced packaging lines to serve the growing demand for heterogeneous integration and fan-out wafer-level packaging (FOWLP).

The parallel investments by Samsung and Amkor in Vietnam signal the country's emergence as a top-tier semiconductor packaging destination, joining the ranks of Taiwan, Malaysia, and South Korea.

What's Driving the Expansion

Several converging factors are fueling this unprecedented investment wave:

1. AI Accelerator Demand
NVIDIA, AMD, and custom AI chip companies require advanced packaging (CoWoS, InFO, chiplet integration) at volumes that exceed current global capacity. Each AI GPU uses 2-4× more advanced packaging area than traditional processors.

2. Chiplet Architecture Adoption
The industry's shift toward disaggregated chiplet designs requires sophisticated packaging that connects multiple dies on a single substrate. This dramatically increases packaging value per chip and requires new high-density substrate and interconnect technologies.

3. Geopolitical Diversification
US-China trade tensions continue driving supply chain diversification. Companies are establishing multi-geography packaging capabilities to reduce concentration risk and comply with export control requirements.

4. Automotive Electronics Growth
Advanced driver assistance systems (ADAS), electric vehicle power management, and in-vehicle computing demand both high-reliability packaging and massive volume scaling.

Implications for PCB and Substrate Manufacturers

The packaging expansion directly impacts the PCB industry:

Advanced substrates (ABF, BT core, glass core) face multi-year supply constraints as packaging capacity outpaces substrate availability
HDI PCB demand increases as more complex SiP (System-in-Package) modules require high-layer-count interposers
Test board complexity grows as packaging facilities need increasingly sophisticated load boards and probe cards
PCB/substrate convergence accelerates—the line between "PCB" and "semiconductor substrate" continues to blur

For PCB manufacturers like AtlasPCB, the packaging boom creates opportunities in IC substrate-like PCB (SLP) technology, high-density test fixtures, and advanced multi-layer boards that serve as interposers between package and system board.

ASE's Hiring Surge

To support this expansion, ASE has launched an aggressive recruitment campaign: 3,000 technical recruits in 2026 and an additional 1,000 in 2027. The hiring focuses on R&D engineers and production scaling specialists—further evidence that the company expects sustained demand growth rather than a cyclical peak.

Sources: TrendForce, Bloomberg, April 2026

Image: Laura Ockel via Unsplash

Originally published at AtlasPCB Engineering Blog

If you're working on designs that require advanced HDI substrates or high-layer-count PCBs for AI/HPC packaging applications, AtlasPCB specializes in complex multilayer boards for semiconductor packaging test and interposer applications. Get a quote →

PCB Supply Chain in May 2026: Why It's Now a Seller's Market

AtlasPCBEngineering — Fri, 08 May 2026 06:16:33 +0000

The PCB industry has officially entered seller's market territory in 2026. NCAB Group's latest supply chain outlook paints a clear picture: rising raw material costs, constrained fabrication capacity, and extended lead times are reshaping procurement strategies across the electronics industry.

The Raw Material Squeeze

Three major input materials are driving costs higher:

Copper: Above $13,300/tonne

Copper prices surged 30%+ year-to-date, driven by AI data center buildout and EV manufacturing competing for supply. For PCB manufacturers, copper represents 25-40% of material costs — meaning a 30% copper price increase translates to 10-15% board cost increases before other factors.

Glass Fiber: Under Quota

Electronic-grade fiberglass faces production quotas limiting availability. Specialty glass for high-speed laminates (NE-glass, spread glass) is even tighter. Capacity additions lag demand by 18-24 months.

Resin Systems

PPE resin shortages continue constraining high-speed laminate production. Epoxy costs elevated by petrochemical inflation and environmental compliance.

Lead Times Are Stretching

The combination of strong demand and material constraints is impacting every PCB category:

Standard 2-4 layer: 2-3 weeks (was 1-2)
6-12 layer multilayer: 3-4 weeks (was 2-3)
HDI (any-layer): 5-7 weeks (was 3-5)
High-speed (Megtron, Rogers): 6-8 weeks (was 4-6)
Rigid-flex: 6-8 weeks (was 4-5)
IC substrates: 16-24 weeks (was 12-16)

What Hardware Teams Should Do Now

NCAB's recommendations for navigating the seller's market:

1. Forecast Earlier

Extend forecast horizons to 12-16 weeks minimum. Place blanket orders for recurring designs. Lock in material allocations early.

2. Design for Availability

Specify alternative material qualifications (e.g., Megtron 6 OR Tachyon 100G). Avoid single-source exotic materials. Design to standard stack-ups matching factory capability.

3. Diversify Suppliers

Qualify at least two manufacturers per board type. Maintain relationships across different regions. Balance cost optimization against supply security.

4. Think Total Cost

The cheapest PCB quote is often most expensive when factoring delivery reliability, quality costs, engineering support, and material traceability.

The Bigger Picture

The global PCB market is projected to reach $95.8 billion in 2026 (Prismark), growing 12.5% year-over-year. This isn't a temporary spike — it's structural demand growth from AI, automotive electrification, and IoT convergence.

For hardware engineers, the practical takeaway: start PCB fabrication conversations during schematic design, not after layout. Build 2-3 week buffers into project schedules versus 2025 timelines. And choose manufacturing partners based on reliability, not just unit price.

Sources: NCAB Group PCB Supply Chain Outlook May 2026, I-Connect007

📌 Originally published at AtlasPCB Engineering Blog

🔗 Need reliable PCB manufacturing with transparent lead times? Get a quote from AtlasPCB — we specialize in high-performance boards for hardware teams navigating supply chain complexity.

AI and ML Hardware Driving Unprecedented Demand for High-Layer-Count PCBs

AtlasPCBEngineering — Thu, 07 May 2026 08:18:08 +0000

The artificial intelligence revolution is transforming the PCB industry in ways few predicted even two years ago. As AI training clusters scale from thousands to hundreds of thousands of GPUs, and inference deployments push into edge computing, the demand for ultra-high layer count PCBs has surged to unprecedented levels.

The Layer Count Arms Race

Modern AI accelerator platforms — including NVIDIA's Blackwell B200/B300 series, AMD's Instinct MI400, and custom ASICs from Google (TPU v6), Amazon (Trainium 3), and Microsoft (Maia 2) — are driving board complexity to new heights.

These platforms share several characteristics that demand high layer counts:

Massive I/O density: A single next-gen GPU package can have 5,000–7,000+ signal pins, each requiring controlled-impedance routing
High-speed serial links: PCIe Gen 6 (64 GT/s PAM4), NVLink, CXL 3.0, and 800G Ethernet each require dedicated stripline routing layers
Power delivery: AI accelerators consuming 700–1000W per chip require multiple power domains with heavy copper planes
Signal integrity: Maintaining signal quality at 56–112 Gbps per lane demands careful stackup design with low-loss materials

The result: server boards for AI clusters now routinely specify 36–48 layers, with leading-edge designs reaching 56–68 layers. This is up from 24–32 layers just three years ago.

Manufacturing Challenges

Boards above 40 layers require:

Advanced X-ray alignment registration (±25µm tolerance)
Pulse-reverse plating for high aspect ratio through-holes (15:1–20:1)
Premium materials (Megtron 6/7, Isola I-Speed) for low-loss transmission
Back-drilling with ±0.1mm accuracy for stub elimination

With 50+ inner layers, even a 1% per-layer defect rate compounds to significant scrap. Fabricators are investing in LDI (Laser Direct Imaging) and AI-powered AOI systems for defect detection.

Supply Chain Implications

The AI hardware boom has tightened supply:

Lead times for 40+ layer boards extended from 15–20 days to 25–35 days
Specialty laminates (low-loss, low-CTE materials) are constrained
Capacity at qualified fabricators is increasingly committed to hyperscaler contracts months in advance

Market Projections

The AI-driven high-layer-count PCB market is projected to grow at 25–30% CAGR through 2028, versus 5–7% for the overall PCB market. Key drivers:

Training cluster expansion (100,000+ GPU clusters)
Edge inference deployment at scale
800G and 1.6T networking switch platforms
HBM interposer substrates and associated PCBs

What This Means for Designers

If you're designing AI/ML hardware, plan for:

Longer lead times — start PCB procurement earlier in the design cycle
Material selection matters — specify low-loss laminates early to ensure availability
DFM review is critical — at 40+ layers, manufacturing feasibility must be validated before tape-out
Partner with capable fabricators — not all PCB manufacturers can handle 50+ layer builds reliably

The convergence of AI demand with advancing PCB technology is creating one of the most dynamic periods in PCB manufacturing history.

For more on high-layer-count manufacturing challenges, read our complete engineering guide. Need a quote for AI platform PCBs? Contact AtlasPCB →

ENEPIG vs ENIG: Which PCB Surface Finish Should You Choose for Wire Bonding?

AtlasPCBEngineering — Thu, 07 May 2026 07:57:03 +0000

Why Surface Finish Matters More Than You Think

PCB surface finish isn't cosmetic — it's a reliability engineering decision that affects solder joint strength, wire bond integrity, contact resistance, and long-term corrosion performance. The wrong choice can cause field failures years after assembly.

Among advanced surface finishes, ENIG (Electroless Nickel Immersion Gold) and ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) are the two dominant options for high-reliability applications. Both provide flat, coplanar surfaces ideal for fine-pitch BGA and wire bonding — but they differ significantly at the nickel-gold interface.

Layer Structure Comparison

ENIG (3 layers)

┌─────────────────────────────────────┐
│ Immersion Gold (1-3 µin)            │ ← Protects Ni
├─────────────────────────────────────┤
│ Electroless Nickel (120-240 µin)    │ ← Barrier layer
├─────────────────────────────────────┤
│ Copper Pad                          │ ← Base metal
└─────────────────────────────────────┘

ENEPIG (4 layers)

┌─────────────────────────────────────┐
│ Immersion Gold (1-3 µin)            │ ← Protects Pd
├─────────────────────────────────────┤
│ Electroless Palladium (4-10 µin)    │ ← Wire bond surface
├─────────────────────────────────────┤
│ Electroless Nickel (120-240 µin)    │ ← Barrier layer
├─────────────────────────────────────┤
│ Copper Pad                          │ ← Base metal
└─────────────────────────────────────┘

The key difference: Palladium deposits autocatalytically (no displacement/corrosion of nickel), while ENIG's immersion gold step inherently attacks the nickel surface.

The Black Pad Problem: ENIG's Achilles Heel

Black pad is a latent defect where the nickel-gold interface is compromised during processing. Pads look normal but contain corroded nickel beneath the gold.

Why it's dangerous:

Visual inspection can't detect it
X-ray can't detect it
Standard testing may pass initially
Failure occurs weeks to months later under thermal cycling
Only destructive cross-sectioning reveals it

ENEPIG solves this by inserting palladium between nickel and gold — gold attacks palladium instead of nickel, and palladium is far more corrosion-resistant.

Wire Bonding: The Clear Winner

Parameter	ENIG	ENEPIG
Gold wire bond	Marginal	Excellent
Aluminum wire bond	Not suitable	Excellent
Process window	Narrow	Wide
Multi-reflow stability	Degrades after 3x	Stable through 5+

ENEPIG's unique advantage: supports both gold and aluminum wire bonding on the same board — essential for mixed-technology assemblies.

When to Choose Which

Choose ENIG when:

Standard SMT assembly only
No wire bonding required
Cost sensitivity is primary concern
Single reflow cycle

Choose ENEPIG when:

Wire bonding (gold or aluminum)
Multiple reflow cycles needed
Press-fit connectors on same board
High-reliability (aerospace, medical, automotive)
Long shelf life required (>12 months)
Black pad risk is unacceptable

Cost Comparison

ENEPIG typically costs 15-30% more than ENIG due to the additional palladium bath. However, for applications where black pad could cause field failures, ENEPIG's premium is negligible compared to warranty costs.

This article is part of our PCB engineering series. For more technical deep-dives on surface finishes, HDI design, and RF PCB manufacturing, visit AtlasPCB.

Need ENEPIG or ENIG boards with IPC Class 3 process control? Get a quote →